The present invention relates generally to compliant interconnects for use in electronic packages and methods for fabricating and designing such compliant interconnects.
Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature sizes, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc. without compromising the microelectronics reliability. Thus, it is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the integrated circuit (IC) feature size will shrink to about 10 nm, and therefore, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Also, as the industry transitions to porous low-K dielectric materials/Cu interconnects to overcome RC delays, it is important to ensure that the stresses induced by the chip-to-substrate interconnects and the package configuration do not crack or delaminate the low-K dielectric material.
Flip chips on organic substrates (FCOBs) with fine-pitch solder bumps are being increasingly used to address performance, power, size, and I/O requirements. FCOBs require underfill to ensure solder bump reliability. However, the added processing costs associated with underfill dispensing and curing, processing challenges especially for fine-pitch assemblies as well as reliability concerns due to underfill delamination make FCOBs a less likely option for future generations of microelectronic packaging. Furthermore, when low-K dielectric material (ultra low-K dielectric in the future) is used in the IC and when such ICs are assembled on organic substrates, the stiff solder bumps could crack or delaminate the low-K dielectric material under thermal excursions. In contrast to flip chip solder bumps, compliant free-standing structures used as chip-to-substrate interconnects can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill material. Similarly, in contrast to second-level solder ball interconnects, compliant free-standing structures used as substrate-to-board interconnects can accommodate the coefficient of thermal expansion (CTE) mismatch between the substrate and the printed circuit board without requiring an underfill material. Also, compliant free-standing structures can be used as interconnects between the die and the printed circuit board. In general, such compliant free-standing structures can be used as an interconnect between two electrical contacts and take up a relative displacement between these contacts. Such free-standing interconnects are referred to as compliant interconnects and do not require an underfill material. Although an underfill material is not required, users can optionally use an underfill material with the compliant interconnects.
Accommodation of CTE mismatch without requiring an underfill, interconnects that do not crack or delaminate the low-K dielectric in the die, fine pitch, and high-yield cost-effective fabrication without compromising the reliability are some of the challenges that off-chip interconnects must address in the future. To address these needs, compliant interconnects can be used. However, given the requirements for higher compliance, lower electrical parasitics, finer pitch, no-underfill and reworkability, compatibility with low-k dielectrics, and cost effective fabrication—there are no compliant interconnects available that meet these requirements simultaneously.
The assignee of the present invention has previously developed a compliant interconnect technology, referred to as G-Helix. This is discussed, for example, by Zhu, Q., Ma, L., and Sitaraman, S. K., “Development of G-helix structure as off-chip Interconnect,” Transactions of the ASME—Journal of Electronic Packaging, Vol. 126, pp. 237-246, June 2004; Lo, G., and Sitaraman, S. K., “G-Helix: Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects,” Proc. of 54th Electronic Components and Technology Conference, Las Vegas, Nev., June 2004, pp. 320-325; and Kacker, K., Lo, G., and Sitaraman, S. K., “Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects” Proc. of. 55th Electronic Components and Technology Conference, Orlando, Fla., 2005, pt. 1, pp. 545-550. The G-Helix compliant interconnect technology is also described in U.S. Pat. No. 6,784,378 assigned to the assignee of the present invention.
G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. Results previously presented by the inventors such as disclosed by Zhu, Q., Ma, L., and Sitaraman, S. K., “Development of G-helix structure as off-chip Interconnect,” Transactions of the ASME—Journal of Electronic Packaging, Vol. 126, pp. 237-246, June 2004, Lo, G., and Sitaraman, S. K., “G-Helix: Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects,” Proc. of 54th Electronic Components and Technology Conference, Las Vegas, Nev., June 2004, pp. 320-325, and Kacker, K., Lo, G., and Sitaraman, S. K., “Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects” Proc. of. 55th Electronic Components and Technology Conference, Orlando, Fla., 2005, pt. 1, pp. 545-550, indicate that it is a promising technology. However, this technology has two drawbacks. First, a three mask fabrication process with three electroplating steps is utilized in the fabrication of G-Helix interconnects. Such a process is relatively expensive and limits the viability of the G-Helix technology. By decreasing the number of masking/electroplating steps the viability of a compliant interconnect technology can be enhanced by improving its cost-effectiveness.
Second, the inductance of the G-Helix interconnect is high and it is desirable to reduce the inductance. A potential solution should achieve both cost-effectiveness and electrical performance without compromising on mechanical performance. Also, a potential solution should be scalable to fine pitch requirements as projected for off-chip interconnects in the ITRS roadmap.
Mechanical performance refers to mechanical compliance and thermo-mechanical reliability of the interconnects. Better electrical performance is qualitatively described in terms of lower resistance and inductance of the interconnects.
It would be desirable to have improved packaging techniques and methods and utilize compliant interconnects with multiple electrical paths in an electronic package. This would improve the mechanical reliability of electronic packages in a cost-effective manner, without compromising on electrical performance.